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1 ? fn7464.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006-2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl29003 light-to-digital out put sensor with high sensitivity, gain selection, interrupt function and i 2 c interface the isl29003 is an integrated light sensors with a 16-bit integrating type adc, i 2 c user programmable lux range select for optimized counts/lux, and i 2 c multi-function control and monitoring capabilities. the internal adc provides 16-bit resolution while rejecting 50hz and 60hz flicker caused by artificial light sources. in normal operation, power consumption is less than 300a. furthermore, an available software power-down mode controlled via the i 2 c interface reduces power consumption to less than 1a. the isl29003 supports a hardware interrupt that remains asserted low until the host clears it through i 2 c interface. designed to operate on supplies from 2.5v to 3.3v, the isl29003 is specified for opera tion over the -40c to +85c ambient temperature range. block diagram features ? range select via i 2 c - range 1 = 0 lux to 1000 lux - range 2 = 0 lux to 4000 lux - range 3 = 0 lux to 16,000 lux - range 4 = 0 lux to 64,000 lux ? human eye response (540nm peak sensitivity) ? temperature compensated ? 16-bit resolution ? adjustable resolution: up to 65 counts per lux ? user-programmable upper and lower threshold interrupt ? simple output code, dire ctly proportional to lux ? ir + uv rejection ? 50hz/60hz rejection ? 2.5v to 3.3v supply ? 6 ld odfn (2.1mmx2mm) ? pb-free (rohs compliant) applications ? ambient light sensing ? backlight control ? temperature control systems ? contrast control ? camera light meters ? lighting controls pinout isl29003 (6 ld odfn) top view ordering information part number (note) package (pb-free) pkg. dwg. # ISL29003IROZ 6 ld odfn l6.2x2.1 ISL29003IROZ-t7* 6 ld odfn l6.2x2.1 ISL29003IROZ-eval evaluation board *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. vdd rext gnd sda scl command register integrating adc data register i 2 c photodiode 1 photodiode 2 mux 3 2 5 6 1 fosc iref counter 2 16 mode gain/range ext shdn int time 4 int interrupt isl29003 timing int 1 2 3 6 5 4 vdd gnd rext sda scl int thermal pad data sheet august 8, 2008
2 fn7464.5 august 8, 2008 absolute maxi mum ratings (t a = +25c) thermal information v dd supply voltage between v dd and gnd . . . . . . . . . . . . . 3.6v i 2 c bus pin voltage (scl, sda) . . . . . . . . . . . . . . . . . -0.2v to 5.5v i 2 c bus pin current (scl, sda) . . . . . . . . . . . . . . . . . . . . . . <10ma int, r ext pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to v dd esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +90c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v dd = 3v, t a = +25c, r ext = 100k 1% tolerance, unless otherwise s pecified, internal timing mode operation (see ?principles of operation? on page 3). parameter description condition min typ max unit v dd power supply range 2.25 3.3 v i dd supply current 0.29 0.33 ma i dd1 supply current disabled software disabled 0.1 1 a f osc1 internal oscillator frequency gain/range = 1 or 2 290 327 360 khz f osc2 internal oscillator frequency gain/range = 3 or 4 580 655 720 khz fi 2 ci 2 c clock rate 1 400 khz data0 diode1 dark adc code e = 0 lux, mode1, gain/range = 1 5 counts data1 full scale adc code 65535 counts data2 diode1 adc code gain/range = 1 accuracy mode1 e = 300 lux, fluorescent light, gain/range = 1 (note 1) 15760 20200 24440 counts data3 diode2 adc code gain/range = 1 accuracy mode2 2020 counts data4 diode1 adc code gain/range = 2 accuracy mode1 e = 300 lux, fluorescent light, gain/range = 2 (note 1) 5050 counts data5 diode2 adc code gain/range = 2 accuracy mode2 505 counts data6 diode1 adc code gain/range = 3 accuracy mode1 e = 300 lux, fluorescent light, gain/range = 3 (note 1) 1262 counts data5 diode2 adc code gain/range = 3 accuracy mode2 126 counts data6 diode1 adc code gain/range = 4 accuracy mode1 e = 300 lux, fluorescent light, gain/range = 4 (note 1) 316 counts data6 diode2 adc code gain/range = 4 accuracy mode2 32 counts v ref voltage of rext pin 0.485 0.51 0.535 v v tl scl and sda threshold lo (note 2) 1.05 v v th scl and sda threshold hi (note 2) 1.95 v i sda sda current sinking capability 3 5 ma i int int current sinking capability 3 5 ma notes: 1. fluorescent light is substitut ed by a white led during production. 2. the voltage threshold levels of the sda and scl pins are vdd dependent: v tl = 0.35*v dd . v th = 0.65*v dd . isl29003
3 fn7464.5 august 8, 2008 principles of operation photodiodes the isl29003 contains two photodiodes. diode1 is sensitive to both visible and infrared light, while diode2 is mostly sensitive to infrared light. the spectral response of the two diodes are independent from one another. see figure 8 spectral response vs wavelength in the performance curves section. the photodiodes convert light to current. then, the diodes? current outputs are conver ted to digital by a single built-in integrating type 16-bit analog-to-digital converter (adc). an i 2 c command mode determines which photodiode will be converted to a digital signal. mode1 is diode1 only. mode2 is diode2 only. mode3 is a sequential mode1 and mode2 with an internal subtra ct function (diode1 - diode2). analog-to-digital converter (adc) the converter is a charge-balancing integrating type 16-bit adc. the chosen method for conversion is best for converting small current si gnals in the presence of ac periodic noise. a 100ms integration time, for instance, highly rejects 50hz and 60hz power line noise simultaneously. see ?integration time or conversion time? on page 8 and ?noise rejection? on page 9. the built-in adc offers the user fl exibility in integration time or conversion time. two timing modes are available; internal timing mode and external timing mode. in internal timing mode, integration time is determ ined by an internal dual speed oscillator (f osc ), and the n-bit (n = 4, 8, 12,16) counter inside the adc. in external timing mode, integration time is determined by the time between two consecutive i 2 c external timing mode commands. see ?external timing mode? on page 7. a good balancing act of integration time and resolution depending on the application is required for optimal results. the adc has four i 2 c programmable range select to dynamically accommodate various lighting conditions. for very dim conditions, the adc can be configured at its lowest range. for very bright condit ions, the adc can be configured at its highest range. interrupt function the active low interrupt pin is an open drain pull-down configuration. the interrupt pin serves as an alarm or monitoring function to determine whether the ambient light exceeds the upper threshold or goes below the lower threshold. the user can also configure the persistency of the interrupt pin. this eliminates any false triggers, such as noise or sudden spikes in ambient light conditions. an unexpected camera flash, for example, can be ignored by setting the persistency to 8 integration cycles. i 2 c interface there are eight (8) 8-bit registers available inside the isl29003. the command and control register s define the operation of the device. the command and control registers do not change until the registers are over written.there are two 8-bit registers that set the high and low interrupt thresholds. there are four 8-bit data read only registers; two bytes for the sensor reading and another two bytes for the timer counts. the data registers contain the adc's latest digital output, and the number of clock cycles in the previous integration period. the isl29003?s i 2 c interface slave address is hardwired internally as 1000100. when 1000100x with x as r or w is sent after the start condition, this device compares the first seven bits of this byte to its address and matches. figure 1 shows a sample one-byte read. figure 2 shows a sample one-byte write. figure 3 shows a sync_iic timing diagram sample for externally controlled integration time. the i 2 c bus master always drives the scl (clock) line, while either the master or the slave can drive the sda (data) line. figure 2 shows a sample write. every i 2 c transaction begins with the master asserting a star t condition (sda falling while scl remains high). the following byte is driven by the master and includes the slave address and read/write bit. the receiving device is responsible for pulling sda low during the acknowledgement period. every i 2 c transaction ends with th e master asserting a stop condition (sda rising while scl remains high). for more information about the i 2 c standard, please consult the philips ? i 2 c specification documents. pin descriptions pin number pin name description 1 vdd positive supply; connect this pin to a regulated 2.5v to 3.3v supply 2 gnd ground pin. the thermal pad is connected to the gnd pin 3 rext external resistor pin for adc reference; co nnect this pin to ground through a (nominal) 100k resistor 4int interrupt pin; lo for interrupt/alarming. the int pin is an open drain. 5scli 2 c serial clock the i 2 c bus lines can be pulled above vdd, 5.5v max. 6sdai 2 c serial data isl29003
4 fn7464.5 august 8, 2008 figure 1. i 2 c read timing diagram sample start w aa aa a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a a6 a5 a4 a3 a2 a1 a0 w a a a a d7d6d5d4d3d2d1d0 a 123456789123456789 123456789123456789 stop stop start sda driven by master device address sda driven by isl29003 data byte0 nak register address i 2 c sda out device address i 2 c data sda driven by master i 2 c clk i 2 c sda in sda driven by master figure 2. i 2 c write timing diagram sample start w aaa a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a b7 b6 b5 b4 b3 b2 b1 b0 a aaa 123456789123456789123456789 stop i 2 c sda in i 2 c clk in sda driven by master functions register address i 2 c sda out device address i 2 c da ta sda driven by master sda driven by master figure 3. i 2 c sync_iic timing diagram sample start w aastop a 6 a 5 a 4 a 3 a 2 a 1 a 0 w a r7 r6 r5 r4 r3 r2 r1 r0 a aa 123456789123456789 register address sda driv en by ma ster i 2 c sda out device address i 2 c da ta i 2 c sda in i 2 c clk in sda driven by master isl29003
5 fn7464.5 august 8, 2008 register set there are eight registers that are available in the isl29003. table 1 summarizes the available registers and their functions. table 1. register set addr (hex) register name bit(s) function name functions/description 00 command 7 enable 0: disable adc-core 1: enable adc-core 6 adcpd 0: normal operation 1: power-down mode 5 timing_mode 0: integration is internally timed 1: integration is externally sync/controlled by i 2 c host 4reserved 3:2 mode<1:0> selects adc work mode 0: diode1?s current to unsigned 16-bit data 1: diode2?s current to unsigned 16-bit data 2: difference between diodes (i1 - i2) to signed 15-bit data 3: reserved 1:0 width<1:0> number of clock cycles; n-bit resolution 0: 2 16 cycles 1: 2 12 cycles 2: 2 8 cycles 3: 2 4 cycles 01 control 7 ext_mode always set to logic 0. factory use only. 6 test_mode always set to logic 0 5 int_flag 0: interrupt is cleared or not yet triggered 1: interrupt is triggered 4 reserved always set to l ogic 0. factory use only. 3:2 gain<1:0> selects the gain so range is 0: 0 to 1000 lux 1: 0 to 4000 lux 2: 0 to 16000 lux 3: 0 to 64000 lux 1:0 int_persist <1:0> interrupt is triggered after 0: 1 integration cycle 1: 4 integration cycles 2: 8 integration cycles 3: 16 integration cycles 02 interrupt threshold hi 7:0 interrupt threshold hi high byte of hi interrupt threshold. default is 0xff 03 interrupt threshold lo 7:0 interrupt threshold lo high byte of the lo interrupt threshold. default is 0x00 04 lsb_sensor 7:0 lsb_sensor read-only data register t hat contains the least si gnificant byte of the latest sensor reading. 05 msb_sensor 7:0 msb_sensor read-only data register t hat contains the most si gnificant byte of the latest sensor reading. 06 lsb_timer 7:0 lsb_timer read-only data register that contains the least si gnificant byte of the timer counter value corresponding to the latest sensor reading. 07 msb_timer 7:0 msb_timer read-only data register that contains the most si gnificant byte of the timer counter value corresponding to the latest sensor reading. isl29003
6 fn7464.5 august 8, 2008 command register 00(hex) the read/write command register has five functions: 1. enable; bit 7. this function either resets the adc or enables the adc in normal operation. a logic 0 disables adc to reset-mode. a logic 1 enables adc to normal operation. 2. adcpd; bit 6. this func tion puts the device in a power-down mode. a logic 0 puts the device in normal operation. a logic 1 powers down the device. for proper shut down operat ion, it is recommended to disable adc first then disable the chip. specifically, the user should first send i 2 c command with bit 7 = 0 and then send i 2 c command with bit 6 = 1. 3. timing mode; bit 5. this f unction determines whether the integration time is done internally or externally. in internal timing mode, integration time is determined by an internal dual speed oscillator (f osc ), and the n-bit (n = 4, 8, 12,16) counter inside the adc. in external timing mode, integration time is det ermined by the time between two consecutive external-sync sync_iic pulse commands. 4. photodiode select mode; bits 3 and 2. this function controls the mux attached to the two photodiodes. at mode1, the mux directs the curr ent of diode1 to the adc. at mode2, the mux directs the current of diode2 only to the adc. mode3 is a sequen tial mode1 and mode2 with an internal subtract function (diode1 - diode2). *n = 4, 8, 12,16 depending on the num ber of clock cycles function. 5. width; bits 1 and 0. this function determines the number of clock cycles per conversion . changing the number of clock cycles does more than ju st change the resolution of the device; it also changes th e integration time, which is the period the device?s analog-to-digital (a/d) converter samples the photodiode current signal for a lux measurement. control register 01(hex) the read/write control register has three functions: 1. interrupt flag; bit 5. this is the status bit of the interrupt. the bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. writing a logic low clears/resets the status bit. 2. range/gain; bits 3 and 2. the full scale range can be adjusted by an external resistor r ext and/or it can be adjusted via i 2 c using the gain/range function. gain/range has four possible values, range(k) where k is 1 through 4. table 9 lists the possible values of range(k) and the resulting fsr for some typical value r ext resistors. table 2. write only registers address register name functions/ description b1xxx_xxxx sync_iic writing a logic 1 to this address bit ends the current adc-integration and starts another. used only with external timing mode. bx1xx_xxxx clar_int writing a logic 1 to this address bit clears the interrupt. table 3. enable bit 7 operation 0 disable adc-core to reset-mode (default) 1 enable adc-core to normal operation table 4. adcpd bit 6 operation 0 normal operation (default) 1 power-down table 5. timing mode bit 5 operation 0 internal timing mode. integration time is internally timed determined by f osc , rext, and number of clock cycles. 1 external timing mode. integration time is externally timed by the i 2 c host. table 6. photodiode select mode; bits 2 and 3 bits 3:2 mode 0:0 mode1. adc integrates or converts diode1 only. current is converted to an n-bit unsigned data.* 0:1 mode2. adc integrates or coverts diode2 only. current is converted to an n-bit unsigned data.* 1:0 mode3. a sequential mode1 then mode2 operation. the difference current is an (n-1) signed data.* 1:1 no operation. table 7. width bits 1:0 number of clock cycles 0:0 2 16 = 65,536 0:1 2 12 = 4,096 1:0 2 8 = 256 1:1 2 4 = 16 table 8. interrupt flag bit 5 operation 0 interrupt is cleared or not triggered yet 1 interrupt is triggered isl29003
7 fn7464.5 august 8, 2008 3. interrupt persist; bits 1 and 0. the interrupt pin and the interrupt flag is triggered/set when the data sensor reading is out of the interrupt threshold window after m consecutive number of int egration cycles. the interrupt persist bits determine m. interrupt threshold hi register 02(hex) this register sets the hi threshold for the interrupt pin and the interrupt flag. by default, the interrupt threshold hi is ff(hex). the 8-bit data written to the register represents the upper msb of a 16-bit value. the lsb is always 00(hex). interrupt threshold lo register 03(hex) this register sets the lo threshold for the interrupt pin and the interrupt flag. by default, the interrupt threshold lo is 00(hex). the 8-bit data written to the register represents the upper msb of a 16-bit value. the lsb is always 00(hex). sensor data register 04(hex) and 05(hex) when the device is configured to output a 16-bit data, the least significant byte is accessed at 04(hex), and the most significant byte can be access ed at 05(hex). the sensor data register is refreshed after every integration cycle. timer data register 06(hex) and 07(hex) note that the timer counter value is only available when using the external timing m ode. the 06(hex) and 07(hex) are the lsb and msb respectively of a 16-bit timer counter value corresponding to the most recent sensor reading. each clock cycle increments the counter. at the end of each integration period, the value of this counter is made available over the i 2 c. this value can be used to eliminate noise introduced by slight timing errors caused by imprecise external timing. microcontrolle rs, for example, often cannot provide high-accuracy command-to-command timing, and the timer counter value can be used to eliminate the resulting noise. calculating lux the isl29003?s output codes, data, are directly proportional to lux. the proportionality constant is determined by the full scale range, fsr, and the n-bit adc, which is user defined in the command register. the proportionality constant can also be viewed as the resolution; the smallest lux measurement the device can measure is . full scale range, fsr, is determined by the software programmable range/gain, range(k), in the command register and an external scaling resistor r ext which is referenced to 100k . the transfer function effectively for each timing mode becomes: internal timing mode external timing mode n = 4, 8, 12, or 16. this is the number of clock cycles programmed in the command register. range(k) is the user defined range in the gain/range bit in the command register. r ext is an external scaling resistor hardwired to the r ext pin. data is the output sensor r eading in number of counts available at the data register. 2 n represents the maximum number of counts possible in internal timing mode. for the external timing mode, the maximum number of counts is stored in the data register named counter. table 9. range/gain typical fsr lux ranges bits 3:2 k range (k) fsr lux range@ r ext = 100k fsr lux range@ r ext = 50k fsr lux range@ r ext = 500k 0:0 1 973 973 1946 195 0:1 2 3892 3892 7784 778 1:0 3 15,568 15,568 31,136 3114 1:1 4 62,272 62,272 124,544 12,454 table 10. interrupt persist bits 1:0 number of integration cycles 0:0 1 0:1 4 1:0 8 1:1 16 table 11. data registers address (hex) contents 04 least-significant byte of mo st recent sensor reading. 05 most-significant byte of most recent sensor reading. 06 least-significant byte of timer counter value corresponding to most recent sensor reading. 07 most-significant byte of timer counter value corresponding to most recent sensor reading. e data = (eq. 1) ------------ = (eq. 2) (eq. 3) fsr range k () 100k r ext ------------------ = (eq. 4) e range k () 100k r ext ------------------ 2 n ---------------------------------------------------- data = (eq. 5) e range k () 100k r ext ------------------ counter ---------------------------------------------------- data = isl29003
8 fn7464.5 august 8, 2008 counter is the number increments accrued for between integration time for external timing mode. gain/range, range (k) the gain/range can be programmed in the control register to give range (k) determining the fsr. note that range(k) is not the fsr (see equation 3). range(k) provides four constants depending on programmed k that will be scaled by r ext (see table 9). unlike r ext , range(k) dynamically adjusts the fsr. this function is especially useful when light conditions are varying drastically while maintaining excellent resolution. number of clock cycles, n-bit adc the number of clock cycles dete rmines ?n? in the n-bit adc; 2 n clock cycles is a n-bit adc. n is programmable in the command register in the width function. depending on the application, a good balance of speed and resolution has to be considered when deciding for n. for fast and quick measurement, choose the smallest n = 4. for maximum resolution without regard of time, choose n = 16. table 12 compares the trade-off between integration time and resolution. see equations 10 and 11 for the relation between integration time and n. see equation 3 for the relation of n and resolution. external scaling resistor r ext and f osc the isl29003 uses an external resistor r ext to fix its internal oscillator frequency, f osc . consequently, r ext determines the f osc , integration time and the fsr of the device. f osc , a dual speed mode oscillator, is inversely proportional to r ext . for user simplicity, the proportionality constant is referenced to fixed constants 100k and 655khz: f osc 1 is oscillator frequency when range1 or range2 are set. this is nominally 327khz when r ext is 100k . f osc 2 is the oscillator frequency when range3 or range4 are set. this is nominally 655khz when r ext is 100k . when the range/gain bits are set to range1 or range2, f osc runs at half speed compared to when range/gain bits are set to range3 and range4. the automatic f osc adjustment feature allows significant improvement of signal-to-noise ratio when detecting very low lux signals. integration time or conversion time integration time is the per iod during which the device?s analog-to-digital adc converter samples the photodiode current signal for a lux measurement. integration time, in other words, is the time to co mplete the conversion of analog photodiode current into a digital signal (number of counts). integration time affects the measurement resolution. for better resolution, use a longer integration time. for short and fast conversions use a shorter integration time. the isl29003 offers user flexibility in the integration time to balance resolution, speed and nois e rejection. integration time can be set internally or externally and can be programmed in the command register 00(hex) bit 5. integration time in internal timing mode this timing mode is programmed in the command register 00(hex) bit 5. most applications will be using this timing mode. when using the internal timing mode, f osc and n-bits resolution determine the integration time. t int is a function of the number of clock cycles and f osc . n = 4, 8, 12, and16. n is the nu mber of bits of resolution. therefore, 2 n is the number of clock cycles. n can be programmed at the command re gister 00(hex) bits 1 and 0. since f osc is dual speed depending on the gain/range bit, t int is dual time. the integration time as a function of r ext and n is: t int1 is the integration time when the device is configured for internal timing mode and gain/range is set to range1 or range2. t int2 is the integration time when the device is configured for internal timing mode and gain/range is set to range3 or range4. table 12. resolution and integration time selection n range1 f osc = 327khz range4 f osc = 655khz t int (ms) resolution lux/count t int (ms) resolution (lux/count) 16 200 0.01 100 1 12 12.8 0.24 6.4 16 8 0.8 3.90 0.4 250 4 0.05 62.5 0.025 4000 r ext = 100k (eq. 6) f osc1 1 2 -- - 100k r ext ------------------ 655 khz = (eq. 7) fosc2 100k r ext ------------------ 655 khz = (eq. 8) f osc 1 1 2 -- - f osc 2 () = t int 2 n 1 f osc ---------- = (eq. 9) for internal timing mode only t int 12 n r ext 327khz 100k ---------------------------------------------- = (eq. 10) t int 22 n r ext 655khz 100k ---------------------------------------------- = (eq. 11) isl29003
9 fn7464.5 august 8, 2008 integration time in external timing mode this timing mode is programmed in the command register 00(hex) bit 5. external timing mode is recommended when integration time can be synchronized to an external signal (such as a pwm) to eliminate noise. for mode1 or mode2 operation, the integration starts when the sync_iic command is sent over the i 2 c lines. the device needs two sync_iic commands to complete a photodiode conversion. the integration then stops when another sync_iic command is received. writing a logic 1 to the sync_iic bit ends the current adc integration and starts another one. for mode3, the operation is a sequential mode1 and mode2. the device needs three sync_iic commands to complete two photodiode measurements. the 1st sync_iic command starts the conversion of the diode1. th e 2nd sync_iic completes the conversion of diode1 and starts the conversion of diode2. the 3rd sync_iic pulse ends the conversion of diode2 and starts over again to commence conversion of diode1. the integration time, t int , is determined by equation 12: i i 2 c is the number of i 2 c clock cycles to obtain the t int. f i 2 c is the i 2 c operating frequency. the internal oscillator, f osc , operates identica lly in both the internal and external timing modes, with the same dependence on r ext . however, in external timing mode, the number of clock cycles per in tegration is no longer fixed at 2 n . the number of clock cycles varies with the chosen integration time, and is limited to 2 16 = 65,536. in order to avoid erroneous lux readings, the integration time must be short enough not to allow an over flow in the counter register. f osc = 327khz*100k /r ext . when range/gain is set to range1 or range2. f osc = 655khz*100k /r ext . when range/gain is set to range3 or range4. noise rejection in general, integrating ty pe adc?s have excellent noise-rejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. for instance, a 60hz ac unwanted signal?s sum from 0ms to k*16.66ms (k = 1,2...k i ) is zero. simila rly, setting the device?s integration time to be an integer multiple of the periodic noise signal greatly impr oves the light sensor output signal in the presence of noise. design example 1 the isl29003 will be designed in a portable system. the ambient light conditions that th e device will be exposed to is at most 500 lux, which is a good office lighting. the light source has a 50/60hz power line noise, which is not visible by the human eye. the i 2 c clock is 10khz. solution 1 using internal timing mode in order to achieve both 60hz and 50hz ac noise rejection, the integration time needs to be adjusted to coincide with an integer multiple of the ac noise cycle times. the first instance of integer values at which t int rejects both 60hz and 50hz is when i = 6, and j = 5. next, the gain/range needs to be determined. based on the application condition given, lux(max) = 500 lux, a range of 1000 lux is desirable. this corresponds to a gain/range range1 mode. also impose a resolution of n = 16-bit. hence, we choose equation 10 to determine r ext . the full scale range, fsr, needs to be determined from equation 3: the effective transfer function becomes: table 13. integration times for typical r ext values r ext (k ) range1 range2 range3 range4 n = 16-bit n = 12-bit n = 12-bit n = 4 50 100 6.4 3.2 0.013 100** 200 13 6.5 0.025 200 400 26 13 0.050 500 1000 64 32 0.125 *integration time in milliseconds **recommended r ext resistor value t int i i 2 c f i 2 c ---------- = (eq. 12) t int 65,535 f osc ----------------- - < (eq. 13) t int i1 60hz ? () j1 50hz ? () = = (eq. 14) t int 61 60hz ? () 51 50hz ? () = = (eq. 15) t int 100ms = for internal timing mode and gain/range is set to range3 or range4 only r ext t int 327khz 100 k 2 n ------------------------------------------------------------ - = r ext 50k = (eq. 16) fsr 1000 lux 100k 50k ------------------ = fsr 2000 lux = (eq. 17) e data 2 16 ------------- 2000 lux = (eq. 18) isl29003
10 fn7464.5 august 8, 2008 solution 2 using external timing mode from solution 1, the desired int egration time is 100ms. note that the r ext resistor only determines the inter oscillator frequency when using external timing mode. instead, the integration time is the time between two sync_iic commands sent through the i 2 c. the programmer determines how many i 2 c clock cycles to wait betw een two external timing commands. i i 2 c = f i 2 c* t int = number of i 2 c clock cycles i i 2 c = 10khz * 100ms i i 2 c = 1,000 i 2 c clock cycles. an exte rnal sync_iic command sent 1,000 cycles af ter another sync_iic command rejects both 60hz and 50hz ac noise signals. next, is to pick an arbitrary r ext = 100k and to choose the gain/range mode. for a maximum 500 lux, range1 is adequate. from equation 3: the effective transfer function becomes: data is the sensor reading data located in data registers 04(hex) and 05(hex) counter is the timer counter value data located in data registers 06(hex) and 07(hex) . in this sample problem, counter = 1000. ir rejection any filament type light source has a high presence of infrared component invisible to the human eye. a white fluorescent lamp, on the other hand has a low ir content. as a result, output sensitivity may vary depending on the light source. maximum attenuation of ir can be achieved by properly scaling the readings of diode1 and diode2. the user obtains data reading from sensor diode1 (d1), which is sensitive to visible and ir, then reading from sensor diode2 (d2), which is mostly sensitive from ir. t he graph in figure 8 shows the effective spectral response after applying equation 19 of the isl29003 from 400nm to 1000nm. equation 19 describes the method of cancelling ir in internal timing mode. where: data = lux amount in number of counts less ir presence d1 = data reading of diode1 d2 = data reading of diode2 n = 1.85. this is a fudge factor to scale back the sensitivity up to ensure equation 4 is valid. k = 7.5. this is a scaling fact or for the ir sensitive diode2. flat window lens design a window lens will surely limit the viewing angle of the isl29003. the window lens should be placed directly on top of the device. the thickness of the lens should be kept at minimum to minimize loss of power due to reflection and also to minimize loss of loss due to absorption of energy in the plastic material. a thickness of t = 1mm is recommended for a window lens design. the bigger the diameter of the window lens, the wider the viewing angle is of the isl29003. table 16 shows the recommended dimensions of the optical window to ensure both 35 and 45 viewing angle. these dimensions are based on a window lens thickness of 1.0mm and a refractive index of 1.59. table 14. solution1 summary to example design problem design parameter value t int 100ms r ext 50k gain/range mode range1 = 1000 lux fsr 2000 lux # of clock cycles 2 16 transfer function table 15. solution2 summary to example design problem design parameter value t int 100ms r ext 100k gain/range mode range1 = 1000 lux fsr 1000 lux # of clock cycles counter = 1000 transfer function e data 2 16 ---------------- - 2000 lux = fsr 1000 lux 100k 100k ------------------ = fsr 1000 lux = e data counter ------------------------------- - 1000 lux = e data counter ------------------------------- - 1000 lux = d3 n d1 kd2 ? () = (eq. 19) d lens ? t d1 d total ? = viewing angle window lens isl29003 figure 4. flat window lens isl29003
11 fn7464.5 august 8, 2008 window with light guide design if a smaller window is desired while maintaining a wide effective viewing angle of the isl29003, a cylindrical piece of transparent plastic is needed to trap the light and then focus and guide the light on to the device. hence, the name light guide or also known as light pipe. the pipe should be placed directly on top of the device with a distance of d1 = 0.5mm to achieve peak performance. the light pipe should have minimum of 1.5mm in diameter to ensure that whole area of the sensor will be exposed. see figure 5. table 16. recommended dimensions for a flat window design d total d1 d lens @ 35 viewing angle d lens @ 45 viewing angle 1.5 0.50 2.25 3.75 2.0 1.00 3.00 4.75 2.5 1.50 3.75 5.75 3.0 2.00 4.30 6.75 3.5 2.50 5.00 7.75 t = 1 thickness of lens d1 distance between isl29001 and inner edge of lens d lens diameter of lens d total distance constraint between the isl29001 and lens outer edge *all dimensions are in mm. d lens t l d lens light pipe isl29003 d 2 d 2 > 1.5mm figure 5. window with light guide/pipe isl29003
12 fn7464.5 august 8, 2008 suggested pcb footprint footprint pads should be a nominal 1-to-1 correspondence with package pads. since ambient light sensor devices do not dissipate high power, heat dissipation through the exposed pad is not important; instead, similar to dfn or qfn, the exposed pad provides robustness in board mount process. intersil recommends mounting the exposed pad to the pcb, but this is not mandatory. layout considerations the isl29003 is relatively insensitive to layout. like other i 2 c devices, it is intended to provide excellent performance even in significantly noisy environments. there are only a few considerations that w ill ensure best performance. route the supply and i 2 c traces as far as possible from all sources of noise. use two power-supply decoupling capacitors, 4.7f and 0.1f, placed close to the device. typical circuit a typical application for the isl29003 is shown in figure 7. the isl29003?s i 2 c address is internally hardwired as 1000100. the device can be tied onto a system?s i 2 c bus together with other i 2 c compliant devices. soldering considerations convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the plastic odfn package does not require a custom reflow soldering profile, and is qualified to +260c. a standard reflow soldering profile with a +260c maximum is recommended. 6 5 4 0.56mm 0.46mm 2.00mm sensor offset 1 2 3 0.29mm 2.10mm figure 6. sensor location drawing figure 7. isl29003 typical circuit vdd 1 gnd 2 rext 3 int 4 scl 5 sda 6 isl29003 r1 10k r2 10k r3 res1 rext 100k c2 0.1f c1 4.7f 2.5v to 3.3v 1.8v to 5.5v microcontroller sda scl i 2 c slave_0 i 2 c slave_1 i 2 c slave_n i 2 c master scl sda scl sda isl29003
13 fn7464.5 august 8, 2008 typical performance curves (r ext = 100k ) figure 8. spectral response figure 9. radiation pattern figure 10. supply current vs supply voltage figur e 11. output code for 0 lux vs supply voltage figure 12. output code vs supp ly voltage figure 13. oscillator frequency vs supply voltage 0 10 20 30 40 50 60 70 80 90 100 300 400 500 600 700 800 900 1k wavelength (nm) normalized response (%) isl29003 d1 isl29003 d2 radiation pattern luminosity angle relative sensitivity 90o 80o 70o 60o 50o 40o 30o 20o 10o 0o 90o 80o 70o 60o 50o 40o 30o 20o 10o 0.2 0.4 0.6 0.8 1.0 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320 306 292 278 264 250 supply current (ma) supply voltage (v) t a = +27c command = 00h 5000 lux 200 lux 2.0 2.3 2.6 2.9 3.2 3.5 3.8 10 8 6 4 2 0 output code (counts) supply voltage (v) t a = +27c command = 00h 0 lux range 2 2.0 2.3 2.6 2.9 3.2 3.5 3.8 1.015 1.010 1.005 1.000 0.995 0.990 output code ratio (% from 3v) supply voltage (v) 5000 lux 200 lux t a = +27c command = 00h 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320.0 319.5 319.0 318.5 318.0 oscillator frequency (khz) supply voltage (v) t a = +27c isl29003
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7464.5 august 8, 2008 figure 14. supply current vs temperature figure 15. output code for 0 lux vs temperature figure 16. output code vs te mperature figure 17. oscillator frequency vs temperature typical performance curves (r ext = 100k ) (continued) -60 -20 20 60 100 315 305 295 285 275 265 supply current (a) temperature (c) v dd = 3v command = 00h 5000 lux 200 lux range 1 range 3 -60 -20 20 60 100 10 8 6 4 2 0 output code (counts) temperature (c) v dd = 3v command = 00h 0 lux range 2 -60 -20 20 60 100 1.080 1.048 1.016 0.984 0.952 0.920 output code ratio (% from +25c) 5000 lux 200 lux v dd = 3v command = 00h temperature (c) range 1 range 3 -60 -20 20 60 100 330 329 328 327 326 325 oscillator frequency (khz) temperature (c) v dd = 3v isl29003
15 fn7464.5 august 8, 2008 isl29003 package outline drawing l6.2x2.1 6 lead optical dual flat no-lead plastic package (odfn) rev 0, 9/06 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.10 index area pin 1 a 2.10 b 2.00 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view typical recommended land pattern ( 6x 0 . 30 ) ( 6x 0 . 55 ) 6 top view (0 . 65) (1 . 95) (0 . 65) (1 . 35) bottom view 6x 0 . 35 0 . 05 b 0.10 ma c 1 1 . 35 1 . 30 ref index area pin 1 6 0.65 0 . 65 max 0.75 6x 0 . 30 0 . 05

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